| 摘要 |
PURPOSE: A delay locked loop(DLL) which noise control is available is provided, which improves tAC even when there is a noise in a clock signal. CONSTITUTION: The first and the second clock buffer(300,310) generate a falling clock signal(fclkt2) and a rising clock signal(rclkt2) respectively by receiving an external clock bar signal(CLKb) and an external clock signal respectively. A clock divider(320) generates a pulse per eight clocks by receiving the rising clock signal. A phase comparator(330) compares a reference signal(ref) from the clock divider with a feedback from a delay model part. A shift controller(340) generates a right shift signal(SR) and a left shift signal(SL), and a shift register(350) controls the amount of delay by receiving the right shift signal and the left shift signal. Delay lines(350,360,370) control the amount of delay by receiving an output signal from the clock divider and the rising clock signal and the falling clock signal respectively in response to an output signal of the shift register. The delay model part(390) compensates a time difference between an external clock and an internal clock. A delay locked loop signal driving part(400) drives an internal circuit by receiving output signals of the second and the third delay line. A low pass filter control part(410) activates a low pass filter, and the first low pass filter(420) counts the number of resulted values from the phase comparator, and the second low pass filter(430) counts the number of resulted values from the phase detector by receiving a low pass filter active signal(lpf_en) from the low pass filter control part and the second and the fourth phase comparison signal(PC1,PC3) from the phase detector.
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