发明名称 |
Ruhestromprüfbarer RAM |
摘要 |
An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An IDDQ-test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits. |
申请公布号 |
DE69429225(D1) |
申请公布日期 |
2002.01.10 |
申请号 |
DE1994629225 |
申请日期 |
1994.08.31 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN |
发明人 |
SACHDEV, MAMOJ |
分类号 |
G11C11/413;G11C11/401;G11C29/00;G11C29/04;G11C29/34;G11C29/50;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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