| 摘要 |
PURPOSE: A method for manufacturing a silicon-on-insulator(SOI) device having a double gate is provided to prevent overlap capacitance between a lower gate and an upper gate, by preventing misalignment between the lower and upper gates. CONSTITUTION: An oxide layer(2) is formed on a silicon substrate(1). A photoresist layer is repeatedly applied, exposed and developed on the oxide layer to form a photoresist layer pattern. The oxide layer is etched by using the photoresist layer pattern so that a trench(3) confining a lower gate formation region is formed. The photoresist layer pattern is removed. The first polysilicon layer is filled in the trench to form the lower gate(4). The first gate oxide layer is formed on the lower gate. A predetermined portion of the oxide layer is etched to form a contact hole exposing a portion of the silicon substrate. A silicon epi layer(7a) is grown in the contact hole and on the oxide layer and the first gate oxide layer. The silicon epi layer is etched back. A lower gate oxide layer(5) and a polysilicon layer are sequentially evaporated on the silicon epi layer. The second polysilicon layer and the second gate oxide layer are patterned by using an exposure mask used in etching the oxide layer for forming the trench. A source/drain region(11) is formed in the silicon epi layer portion at both sides of the upper gate(10).
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