| 摘要 |
PURPOSE: A method for manufacturing a complementary-metal-oxide-semiconductor(CMOS) transistor is provided to improve a short channel margin, by forming shallower source/drain regions for an n-type MOS transistor and a p-type MOS transistor than that of a conventional technology. CONSTITUTION: The first and second conductive wells(32,33) are formed in a substrate(31). The first and second gate electrodes(36a,36b) are formed on the first and second conductive wells by interposing respective gate insulation layers. The second conductive impurity region(37) of a low density is formed in the first conductive well at both sides of the first gate electrode. The first conductive impurity region(38) of a low density is formed in the second conductive well at both sides of the second gate electrode. An insulation layer sidewall is formed on the substrate at both sides of the first and second gate electrode. The second conductive impurity region is formed on the first conductive well at both sides of the first gate electrode including the insulation layer sidewall. A silicide layer is formed on the first and second conductive impurity regions of the low density and the first and second gate electrodes. The first conductive impurity region of a high density is formed in the second conductive well at both sides of the second gate electrode including the silicide layer.
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