SEMICONDUCTOR MEMORY DEVICE HAVING ADDRESS SKEW FREE CIRCUIT

摘要

PURPOSE: A semiconductor memory device having an address skew free circuit is provided, which can prevent cell data loss by preventing a plurality of memory cells from being selected as an address skew permission range increases. CONSTITUTION: A memory cell array(9) has a plurality of memory cells connected to a plurality of word lines(WL) and a plurality of bit lines(BL), and one memory cell comprises one transistor and one capacitor. A row decoder(8) selects one of the word lines by decoding a row address signal, and a column decoder(11) selects one of the bit lines through a column gate(12) by decoding a column address signal. A write or a read operation mode is determined by a logic state of a write enable signal(WEB) applied to an I/O gate(13). An address transition sensing circuit(2) generates an ATD pulse by sensing the change of an address being output from an address buffer(1). A pulse extension circuit(3) generates a pulse extended signal ATDD by extending the ATD pulse. An ending edge pulse circuit(4) generates a normal operation enable pulse(NRE) by detecting an ending edge of the extended pulse signal ATDD. A pulse extension and OR gate circuit(5) further extends the extended pulse signal ATDD and generates an NERFH signal by OR-gating.