SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, TEST PATTERN GENERATING METHOD FOR IT, METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT TESTING DEVICE

摘要

PROBLEM TO BE SOLVED: To solve the problem that, if an output value changes relative to a clock cycle, increase of a test pattern and a tester operating faster than operation frequency of a semiconductor integrated circuit are required for realizing test for it. SOLUTION: An output signal is branched for an output terminal 209 whose output value changes relative to the cycle of a clock CLK supplied to an LSI201, and applied with an appropriate delay amount from a delay circuit 211. Thus, an output pattern which intrisically changes at different times is changed to the output pattern changing at the same time, which is used as an expected value pattern, resulting in reduced test pattern and testing with a low-cost slow tester.