发明名称 |
Electrically erasable and programmable semiconductor memory |
摘要 |
A first transistor is connected between the gates of select transistors connected to two ends of a memory cell and a select line control circuit. A first gate line is connected to the gate of the first transistor. A first voltage control circuit controls the voltage of the first gate line to turn on or off the first transistor. A second transistor is connected between the control gate of the memory cell and a word line control circuit. A second gate line separated from the first gate line is connected to the gate of the second transistor. A second voltage control circuit controls the voltage of the second gate line to turn on or off the second transistor.
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申请公布号 |
US6337807(B2) |
申请公布日期 |
2002.01.08 |
申请号 |
US20000749737 |
申请日期 |
2000.12.28 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
FUTATSUYAMA TAKUYA;IMAMIYA KENICHI;IKEHASHI TAMIO |
分类号 |
G11C16/06;G11C16/08;(IPC1-7):G11C16/04 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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