发明名称 Method of producing a vertical MOS transistor
摘要 A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.
申请公布号 US6337247(B1) 申请公布日期 2002.01.08
申请号 US20000487411 申请日期 2000.01.18
申请人 INFINEON TECHNOLOGIES AG 发明人 SCHULZ THOMAS;äUGLE THOMAS;ROESNER WOLFGANG;RISCH LOTHAR
分类号 H01L21/336;H01L29/78;(IPC1-7):H01L21/336 主分类号 H01L21/336
代理机构 代理人
主权项
地址