| 摘要 |
A Viterbi decoder for Viterbi-decoding an input signal, includes a path memory, a shift register, and a traceback circuit. The shift register has at least (constraint length -1) bits as the number of stages. The traceback circuit inputs, to the shift register, the AND per bit between a signal generated by a decoder connected to the shift register and the content of the path memory designated by a traceback address counter.
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