| 摘要 |
A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently "self-aligned" to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.
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