| 摘要 |
A multilayer wiring board for mounting a semiconductor chip or a semiconductor device, in which the number of wiring layers in minimized, having a plurality of wiring layers, in which each of said wiring layers includes lands arranged in the form of a square lattice and wiring patterns each having one end connected to one of said lands and the other end extending outward beyond an outermost row of said lattice, said lands having a land pitch p and a land diameter d and said wiring patterns having a pattern width w and an interpattern space s, said p, d, w, and s satisfying the following relationship:andwherein said lattice has periodic land-free or vacant lattice sites, all lands in said outermost row have wiring patterns extending outward therefrom, and said land-free or vacant lattice sites provide a space through which wiring patterns extend outward therefrom, and said land-free or vacant lattice sites provide a space through which wiring patterns extend outward from, and are connected to, lands of an inner row.
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