| 摘要 |
A semiconductor memory device including a redundancy circuit having latch cells is provided. In the semiconductor memory device, memory cells are selected in memory cell blocks each having a plurality of memory cells arrayed in columns and rows. Data of the selected memory cells is input to or output from the memory cell blocks via data lines. The semiconductor memory device includes a row decoder, a sub word line driver, latch cells, fuse boxes, a latch cell control unit, and a switch unit. The row decoder decodes a row address and generates a word line enable signal for selecting the word lines of a group of memory cells among memory cells. The sub word line driver is connected to the word line enable signal, and drives the selected memory cells. The latch cells are arranged along the data lines. Each of the fuse boxes has a plurality of fuses which are programmed in accordance with a defective cell address in the memory cell block. The latch cell control unit generates a latch cell selection signal in response to the output signal of each of the fuse boxes, and selects latch cells. The switch units connect the selected latch cells to the data lines in response to the latch cell selection signal.
|
