| 摘要 |
A phase delay arrangement for connecting high speed digital ICs, wherein a substantial majority of delay is provided via added passive delay elements. The phase synchronization delay arrangement (circuit connection, system and method) adds delay to the signal propagation path between a driving circuit 110 and receiving circuit 130, in order to match signal propagation between a transmitting/receiving circuit pair. Such phase synchronization delay arrangement is provided substantially by added passive components or devices, e.g., added signal line length, inductors, capacitors, which provide a majority or mainstay of the delay, but can further include single ones of flow-through latches, drivers, and programmable delay lines.
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