| 摘要 |
An apparatus for joint synchronization of digital communication signals from multiple receive channels comprises a control unit, a metric computer, and a decimator. The control unit generates test sampling phase vectors for use in decimating the signals. The output of the decimator is used by the metric computer to form a metric predictive of the performance of a demodulator. The metric is used by the control unit to select an optimal sampling phase vector. In one embodiment, the metric computer calculates the signal to impairment plus noise ratio (SINR) at the output of the demodulator based on the decimated signals. In one embodiment, a data correlation estimator generates a data correlation estimate for use in calculating output SINR.In another embodiment, the apparatus includes a select unit and a metric computer. The select unit may include a control unit and a decimator. The metric computer also includes at least one decimator. Test sampling phase vectors are provided to the metric computer along with the input signals. The metric computer generates a metric predictive of the performance of the interference canceling processor. The control unit selects a test sampling phase vector that optimizes performance of the interference canceling processor. The decimator decimates the input signals according to the sampling phases of the selected sampling phase vector.A method of joint synchronization of signals from multiple receive channels is also disclosed.
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