| 摘要 |
A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.
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