Interprocessor communication interface with message unit coupled to next interface and to internal receive and send buffer

摘要

An interprocessor communication device, in which a plurality of processors are interconnected to processor buses for an address signal, a data signal, and a control signal, receiving/outputting handshake signals for transmitting/receiving a message to/from an adjacent processor. A plurality of memory blocks are connected to memory buses for an address signal, a data signal, and a control signal and stores/outputs data upon input of an address signal and a control signal. A rotation bus interface module, connected between the processor buses and the memory buses, switches the memory buses connected to the processor buses in response to handshake signals received from two adjacent processors to allow the processors exclusively to access the memory blocks.