发明名称 |
Semiconductor memory device including spare memory cell |
摘要 |
A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.
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申请公布号 |
US6335886(B1) |
申请公布日期 |
2002.01.01 |
申请号 |
US20000725149 |
申请日期 |
2000.11.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OCHI TAKEHIRO;KOBASHI HISAO |
分类号 |
G06F12/16;G11C11/401;G11C11/408;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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