DYNAMICALLY CONFIGURABLE PROCESSOR CORE AND METHOD FOR MAKING THE SAME

摘要

A dynamically configurable processor core and a method for making the same. A processor core is implemented in a field-programmable gate array (FPGA). The processor core (10) includes a memory (24), an instruction register (14), a register signal circuit, a register file (12), and an arithmetic logic unit (ALU). The memory responds to write and read instructions to respectively store and read and produce address and data signals. The instruction register receives and holds stored address and data signals in response to the signals. The register signal circuit produces register signals in response to the stored and held address and data signals. The register file receives the register signals, as well as index registration and signal write instructions and produces information including the data signals stored in the memory. The ALU receives the information and produces the address signals received by the memory and by the register signal circuit.