发明名称 Serial access memory and data write/read method
摘要 An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD,/WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.
申请公布号 US2001055022(A1) 申请公布日期 2001.12.27
申请号 US20010773024 申请日期 2001.02.01
申请人 YOSHIOKA SHIGEMI 发明人 YOSHIOKA SHIGEMI
分类号 G11C11/401;G11C7/10;G11C29/34;(IPC1-7):G09G5/36;G11C7/00 主分类号 G11C11/401
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