SELF-ISOLATED GATE OXIDATION FOR AN INTEGRATED CIRCUIT VERTICAL DEVICE

摘要

A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a <100> crystal plane sidewall (212) is used for the channel region, and <110> crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.