发明名称 CORRELATED DOUBLE SAMPLING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To realize a correlated double sampling circuit that solves the problem of settling time after a sample-and-hold circuit and excludes fluctuations in an output level due to a droop characteristic of the sample-and-hold circuit at a variable rate. SOLUTION: This correlated double sampling circuit is provided with a 1st analog/digital converter that receives an output of a CCD image sensor and samples the output for a field-through period of the sensor, a 2nd analog/ digital converter that receives the output of the CCD image sensor and samples the output for a signal output period of the sensor, and a subtractor that subtracts outputs of the 1st and 2nd analog/digital converters.
申请公布号 JP2001358992(A) 申请公布日期 2001.12.26
申请号 JP20000181659 申请日期 2000.06.16
申请人 YOKOGAWA ELECTRIC CORP 发明人 NARUKAWA KENICHI
分类号 H04N5/335;H04N5/357;H04N5/363;H04N5/378;(IPC1-7):H04N5/335 主分类号 H04N5/335
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