| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock signal distributing circuit for distributing a clock signal having a 1:1 duty ratio in the same timing. SOLUTION: Invertors 2, 3, 4, and 5 connected like a tree and having an even number of stages are designed so that the delay timeαat the time of buildup can be made equal and that a delay timeβat the time of decay can also be made equal. When a clock signal CK having a 1:1 duty ratio is inputted to the input side of the inverter 2 of the first stage, a clock signal having a 1:1 duty ratio is outputted from the inverter 5 in the fourth stage with a 2(α+β) delay, and supplied to the clock terminal C of a FF(flip flop) 6 being a sequential circuit element in an integrated circuit.</p> |
