发明名称 |
APPARATUS AND METHOD FOR SYNCHRONOUS ACQUISITION |
摘要 |
PROBLEM TO BE SOLVED: To enable efficient identification of scrambling codes of a plurality of paths and to search a cell at a faster speed than that of prior art. SOLUTION: A first step processor 105 detects a plurality of slot timing, corresponding to a plurality of correlated values of a threshold or larger. A second step processor 110 detects scrambling code timing and scrambling code group, according to anyone slot timing of a plurality of the slot timing. A third step processor 115 identifies the scrambling code in accordance with scrambling code timing. A controller 104 switches a switch 103, so that the process of the second processor 110 and the process of the third processor 115 are conducted for the plurality of the slot timing at each time of the process in the first processor 105. |
申请公布号 |
JP2001358612(A) |
申请公布日期 |
2001.12.26 |
申请号 |
JP20000177642 |
申请日期 |
2000.06.13 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
AIHARA KOICHI;SOUMON JUNJI;IMAIZUMI MASARU;MINAMIDA TOMOAKI;SUZUKI HIDETOSHI |
分类号 |
H04B1/707;H04B1/7083;H04B7/26;H04L7/00;H04W48/16 |
主分类号 |
H04B1/707 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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