发明名称 JIG STRUCTURE FOR ASSEMBLING AND MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF ASSEMBLING THE SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To remove faults generated by the inclination of a shelf in the conventional sealing process of a liquefied resin, on which a tray for baking installed in a baking furnace is positioned. SOLUTION: The sealing process, using the liquefied resin for the semiconductor device uses, a horizontal base, having a structure in which through-holes having three screw threads are formed into thick horizontal plates (35), which hardly deform by heat, and three balancing-adjusting screws (34) are driven into the holes when a semi-finished product, on which a semiconductor chip is loaded, is coated with sealing resin and the sealing resin is thermoset in the baking furnace. The horizontal base and the mounting surface of the baking furnace can be balanced, by adjusting the length of the balancing-adjusting screws projected from the horizontal plates. The tray for baking, on which the semi-finished product is placed, is loaded on the horizontal base, and the resin is thermoset by baking in the baking furnace. Accordingly, the surface of the sealing resin can be leveled.
申请公布号 JP2001358159(A) 申请公布日期 2001.12.26
申请号 JP20000177310 申请日期 2000.06.13
申请人 NEC CORP 发明人 SUZUKI KATSUNOBU
分类号 H01L21/50;H01L21/56;(IPC1-7):H01L21/56 主分类号 H01L21/50
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