| 摘要 |
A memory allocator employs a programmable and controllable switching circuit which switches multiple address buses and multiple data buses connected to the digital signal processing unit to differing banks of memory depending upon determined system requirement data, such as the amount of program memory and data memory necessary for a particular application. The memory space may be separate banks of memory incorporated into pools of memory if desired. The controllable switching circuit multiplexes the appropriate address bus and data bus to a given memory block or blocks which may be independent and can still be dedicated to specific application tasks. The memory banks are normal single address port and single data-port banks but are allowed to be connected to multiple data buses and address buses through the switching circuit. The switching circuit is sized to allow access to a subset of banks in a pool of banks associated with a given memory port. The digital signal processor is a multi-port device.
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