| 摘要 |
A coprocessor coupled to a hardware processor and capable of performing multimedia operations is provided. The coprocessor includes an instruction fetch and decode unit which is coupled to a plurality of execution units including an integer execution unit and a multimedia execution unit. The coprocessor includes a superscalar architecture and each of the execution units includes a plurality of pipelined stages. Accordingly, the multimedia execution unit has several integer execution units which can be executed in parallel for improved multimedia performance. A visible register set is coupled to the integer execution unit for receiving operands to initialize operation of the coprocessor. Further, a first register file is coupled to the multimedia execution unit and a second register file is coupled to the integer execution unit. A memory bus coupled to memory and the integer execution unit is used for accessing data and multimedia applications in memory as indicated by values in the visible register set.
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