发明名称 |
Semiconductor memory device permitting improved integration density and reduced accessing time |
摘要 |
A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.
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申请公布号 |
US6333884(B1) |
申请公布日期 |
2001.12.25 |
申请号 |
US19990311560 |
申请日期 |
1999.05.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KATO HIROSHI;OOISHI TSUKASA;HIDAKA HIDETO |
分类号 |
G11C11/41;G11C5/02;G11C5/06;G11C7/06;G11C7/10;G11C7/18;G11C11/401;G11C11/409;G11C11/419;(IPC1-7):G11C7/02 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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