| 摘要 |
<p>PURPOSE:To increase the speed of reading operation by obtaining an output control pulse signal, by which timing is not displaced regardless of the level of an address signal, when chip enable-access is conducted and equalizing a chip enable-access-time at a time when the address signal is at L to a chip enable-access-time at a time when the address signal is at H. CONSTITUTION:An address pulse signal passing control circuit 200 is mounted between an address pulse generating circuit 6 and an output control pulse signal generating circuit 14. Passage through the output control pulse signal generating circuit 14 is interrupted regarding an address pulse signal ADDP generated when chip enable-access is conducted.</p> |
