| 摘要 |
The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is "merged" with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.
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