发明名称 PIPELINE-TYPE A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To obtain highly accurate A/D conversion output even if the resolution of A/D conversion is set to 16 bits by eliminating an integration error. SOLUTION: During first and second periods, a signal-processing circuit 32 samples an analog signal from a previous stage by capacitors C11 and C12 and then uses either of the capacitors C11 and C12 as the feedback element of an operational amplifier 34. Then, the operational amplifier 34 performs the addition and subtraction of an analog signal that is sampled by remaining capacitors and the output of a reference voltage generation circuit 31. Then, either of the capacitors C11 and C12 is selected to be a feedback element so that the integration error can be eliminated.
申请公布号 JP2001352244(A) 申请公布日期 2001.12.21
申请号 JP20000169860 申请日期 2000.06.07
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 SUNAHARA MITSUE
分类号 H03M1/14;(IPC1-7):H03M1/14 主分类号 H03M1/14
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