发明名称 DEVICE AND METHOD FOR ANALYSING FAILURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To analyze a failure of semiconductor integrated circuit capable of easily specifying failure position and failure layer. SOLUTION: This failure analyzing device is provided with a means for coating the surface of the semiconductor integrated circuit with liquid crystal, a means 1 for providing an operation state, a means 2 for detecting variation of refractive index of the liquid crystal due to heat generation in the operation state, and a means 4 that cuts the shorter edge side of a wire on a layout in a variation region, has a dummy pad for verifying on the longer edge side, and performs electrical verification, and specifies the failure position and the failure layer. The means 4 for electrical verification isolates the refractive index varying region on the layout, performs wiring after disconnection, disconnects a layout pattern in a failure region specified by using the variation of refractive index of the liquid crystal due to heat generation from others, and discriminates whether or not the variation of refractive index of the liquid crystal due to heat is caused by current on the circuit or a short circuit by providing a dummy opening state.
申请公布号 JP2001349931(A) 申请公布日期 2001.12.21
申请号 JP20000173070 申请日期 2000.06.09
申请人 NEC YAMAGATA LTD 发明人 SATO TOSHIHIRO
分类号 G01R1/06;G01N21/956;G01R31/302;G06T1/00;H01L21/66 主分类号 G01R1/06
代理机构 代理人
主权项
地址