| 摘要 |
The memory cell structure of read-only type (20) with a double gate comprises the source (S), the drain (D), the floating gate (GF) and the control gate (GC), where the floating gate is formed by a standard gate (30) coupled to the first conducting electrode (31), which is similar to the first electrode (3) of the capacitor of DRAM cell (1), and the control electrode formed by the second conducting electrode (33) separated from the first electrode by an insulating layer (32), which is similar to the second electrode (5) of the capacitor separated from the first plate by an insulating layer (4). The manufacturing method includes a simultaneous formation of the double-gate structure of read-only type such as EPROM, EEPROM, or Flash-EEPROM, and the standard gate structure of type DRAM. The first electrode is formed of rough polycrystalline silicon. The manufacturing method comprises the steps: (a) The formation of the drain (D), the source (S), and the gate (G, 30) for each of the two cells. (b) The formation of the first electrode (3) as the first plate of capacitor, and simultaneously the electrode (31) of the double-gate cell. (c) The deposition of an insulating layer (4), and simultaneously of an insulating layer (32). (d) The formation of the second electrode (5) as the second plate of capacitor, and simultaneously of the electrode (33), which is the control gate (CG) of the double-gate cell. The insulating layer (32) is of a greater thickness than the insulating layer (4). The step (d) comprises two phases, the deposition of electrode (5) and the deposition of electrode (33), for the optimization of characteristics of the two cells. An integrated circuit is also claimed which comprises the double-gate cell, or the associated cell s.
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