| 摘要 |
PROBLEM TO BE SOLVED: To provide a small scale alarm detecting circuit which detects an alarm (AIS) when m bits of an input signal are continuously '1' while allowing n error bits in m bits. SOLUTION: The alarm (AIS) detecting circuit comprises n cascaded counters 10a, 10b,..., 10n receiving an input signal DATA and an input clock CLK, and a flip-flop 12 connected to the output side of the counter 10n. When '1' continues in the input signal DATA, the count is added by the input clock CLK and when the input signal DATA is '0', output value of a prestage counter (initial stage counter is '0') is read out. When a maximum count (m-n) is reached, decode output is brought to '1'. |
