| 摘要 |
PROBLEM TO BE SOLVED: To reduce the area of a memory cell and to simplify manufacturing process by fine patterning in a semiconductor memory device, having an erasing gate electrode. SOLUTION: A floating gate electrode 105 is formed in a letter U in cross section, along the sidewalls of two neighboring device isolating insulating films 103 and the surface of a gate insulating film 104. A control gate electrode 107 is formed long, between the two neighboring device which isolates insulating films 103 in the same direction of the device isolating insulating film 103 and is buried in the U-shaped cross section of the floating gate electrode 105 in a region where the floating gate electrode 105 exists and is buried between the device isolating insulating films 103, in the region where the floating gate electrode 105 does not exist. The surface of the control gate electrode 107 can be made substantially equal in height to that of the floating gate electrode 105, and the erasing electrode 110 can be reduced in height.
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