发明名称 DESIGN SUPPORT DEVICE FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To quickly arrange a non-logic cell for reducing the electromagnetic radiation of a semiconductor device at design. SOLUTION: A layout means 1a lays out logic cells and a wiring pattern for connecting the logic cells. A means 1b detects a site to be arranged, that does not include any logic cells and forbidden regions, after layout is completed by the means 1a. A means 1d stores the pattern of the non-logic cell. A means 1c detects a site, containing only the forbidden region. A means 1e arranges the non-logic cell to the site to be arranged, compares the arrangement state of the forbidden area with the pattern of the non-logic cell in the site containing the forbidden region, and arranges the non-logic cell merely to a site, where they do not interfere mutually.
申请公布号 JP2001351979(A) 申请公布日期 2001.12.21
申请号 JP20000168009 申请日期 2000.06.05
申请人 FUJITSU LTD 发明人 KURODA SACHI;SUGIOKA TOSHIAKI;OSAJIMA TOORU;ICHINOSE SHIGENORI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/82 主分类号 G06F17/50
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