| 摘要 |
PROBLEM TO BE SOLVED: To easily and speedily generate a test pattern series for detecting a delay failure, and a disconnection failure accompanied with delay in an IC. SOLUTION: Positions (failures) such as a logic gate and a signal line in a circuit that may fail are listed up (101), an initializing test pattern v1 for selecting one of the failures and setting an initial value for activating the failure on the position is determined by an implication operation (103), a propagation test pattern v2 for propagating a degeneracy failure to a next stage gate is determined by an implication operation (105), the series of the v1 and v2 are registrated in a test pattern list (107), and the processes discussed above are repeated until unprocessed failure in the failure list is eliminated.
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