HIGH-K GATE DIELECTRIC PROCESS WITH SELF ALIGNED DAMASCENE CONTACT TO DAMASCENE GATE AND A LOW-K INTER LEVEL DIELECTRIC

摘要

A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.