发明名称 METHOD FOR CREATING AN INTEGRATED CIRCUIT STAGE WHEREIN FINE AND LARGE PATTERNS COEXIST
摘要 <p>The invention concerns a method which consists in successively using a radiation-sensitive resin layer at sites (4') designed to form large semiconductor patterns in a still intact layer (2), beneath at least a hard mask (3'), then a resin layer sensitive to particle bombardment (6) above the fine patterns to be formed in that same layer (2) which can be juxtaposed with the former. The first resin patterns are collectively and rapidly exposed by an exposure, while the electron bombardment enables to form fine patterns with great accuracy. Another hard mask (9) has been deposited before (6) the second resin (6) and forms flanks (10) around the large patterns, protecting them from lateral attacks during etching.</p>
申请公布号 WO2001096957(A1) 申请公布日期 2001.12.20
申请号 FR2001001850 申请日期 2001.06.14
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