| 摘要 |
<p>Clock generation circuitry (1300) includes an oscillator (1302) for generating a first signal from a crystal (1301) of a selected oscillating frequency. A first frequency multiplier (1304) selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider (1305) selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency. A second frequency multiplier (1304) selectively multiplies the frequency of the third signal by a third factor to obtain a fourth signal of a selected frequency, the second and third factors selected to produce a fourth signal having a frequency of a preselected multiple of a second set of clock signals.</p> |
