发明名称 |
Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein |
摘要 |
In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.
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申请公布号 |
US2001052602(A1) |
申请公布日期 |
2001.12.20 |
申请号 |
US20010922669 |
申请日期 |
2001.08.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FURUTANI KIYOHIRO;KONISHI YASUHIRO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/4076;G11C11/409;(IPC1-7):H01L31/072 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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