Circuit for routing input signal to parallel circuit branches has queue function and clock-delayed reproduction of output signal

摘要

In each circuit branch, a queue function is provided between an input stage and an output stage for the logic circuits (UG3,OG2,UG4,OG3) receiving the signals from the input stage. The signals from the input stages (CI1,CI2) are logically combined so that a displaced clock-controlled reproduction of the output signals from the two output stages (CO1,CO2) is performed.