| 摘要 |
A memory device 10 which is operable to receive an input signal and to generate an corresponding data bearing output signal in response. The device includes an series of circuit stages 200 operable to be triggered by the input signal at a first stage, stage 1, of the series. The signal then causes sequential triggering of stages along the series to a last stage of the series to generate the output signal. The data is represented in time durations taken for each stage in the series to trigger a subsequent stage in the series. Sequential triggering of the stages generates a data bearing output signal for output from the device 10. The device 10 can be modified to repetitively output the data in response to the input signal. The device (fig.8, 900) can be adapted to provide a delay before repeating the data, thereby coping with contention when several devices (fig. 8, 900) are operating within range of one another. |
