| 发明名称 |
METHOD OF MAKING A HIGH-VOLTAGE TRANSISTOR WITH MULTIPLE LATERAL CONDUCTION LAYERS |
| 摘要 |
<p>A method for making a high voltage insulated gate field-effect transistor having a source region (14) and a drain region (19,17) comprises the steps of forming the drain region with an extended well region (17) having a buried layer (18) of opposite conduction type implanted therein. The buried layer creates an associated pair of parallel JFET conduction channels (24,25) in the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the field-effect transistor with a low on-state resistance.</p> |
| 申请公布号 |
EP1163697(A1) |
申请公布日期 |
2001.12.19 |
| 申请号 |
EP20000908424 |
申请日期 |
2000.01.31 |
| 申请人 |
POWER INTEGRATIONS, INC. |
发明人 |
RUMENNIK, VLADIMIR;DISNEY, DONALD, R.;AJIT, JANARDHANAN, S. |
| 分类号 |
H01L29/78;H01L21/266;H01L21/336;H01L21/74;H01L29/06;H01L29/08;H01L29/10;H01L29/40;H01L29/417;H01L29/423;(IPC1-7):H01L21/425;H01L21/265;H01L29/80;H01L29/808;H01L27/085;H01L29/88;H01L29/94;H01L29/76;H01L21/823;H01L27/02 |
主分类号 |
H01L29/78 |
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