PROCESSOR HAVING A COMPARE EXTENSION OF AN INSTRUCTION SET ARCHITECTURE

摘要

A processor having a compare extension and a conditional branch extension (630) of an instruction set architecture (320) which incorporates a set of high performance floating point operations. The instruction set architecture (320) incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The compare extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and a paired-single floating point format. The conditional branch extension (630) includes instructions directed to branching if, for example, either one of the two condition codes (635) is false or true, if any of three condition codes (630) are false or true, or if any one of four condition codes (630) are false or true.