| 摘要 |
PROBLEM TO BE SOLVED: To integrate clocks of a semiconductor device having a SDRAM and an ASIC to one clock. SOLUTION: A LSI tester 20 inputs test data to an ASIC 13 based on an internal clock generated by a clock generating circuit 11 of a SDRAM 12, and takes out test result data from the ASIC 13. A skewness adjusting device 21 is connected to both of a clock wiring 30 and a data wiring 31 at the time of test so that the timing of a clock and data is made the same as internal signal transmitting timing at the time of normal operation, and its equivalent parasitic capacity is adjusted. Clocks of the SDRAM and the ASIC are integrated to one by enabling a test by a common internal clock.
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