| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for automatically wiring a semiconductor integrated circuit which contrives to restrict generation of an upper and lower restriction in a wiring design of the semiconductor integrated circuit, and shortens the time required for layout design, and enables to decrease the size of the semiconductor integrated circuit and increase the speed thereof. SOLUTION: This method comprises the steps of: congestion of a schematic wiring lattice set in S105 is made uniform (S103); determining a vertical direction detailed wiring route based on the schematic wiring route in S103 (S110); determining a horizontal direction detailed wiring route based on the vertical direction detailed wiring route in S110 (S111); further extracting a vertical direction segment belonging to a vertical direction schematic wiring region in the vertical direction detailed wiring step in S110 (S112); bisecting the vertical direction schematic wiring region up to a wiring track level (S113, S114); updating a wiring congestion every division (S115); allocating a vertical direction segment to a new division region at every division (S116); and forming a horizontal direction segment when the division of the vertical direction segment in S116 is generated (S117).
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