发明名称 |
Buffer for varying data access speed and system applying the same |
摘要 |
A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.
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申请公布号 |
US2001052057(A1) |
申请公布日期 |
2001.12.13 |
申请号 |
US20010878896 |
申请日期 |
2001.06.11 |
申请人 |
LAI JIIN;CHEN CHIA-HSIN;CHANG NAI-SHUNG |
发明人 |
LAI JIIN;CHEN CHIA-HSIN;CHANG NAI-SHUNG |
分类号 |
G11C7/10;(IPC1-7):G06F12/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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