| 摘要 |
AVLIW processor has multiple pipelines (410, 425) for execution of subcommands of VLIW instructions in parallel. Each pipeline has at least one execution stage (412, 414) and a trap stage (422, 430). At least one can operate on operands of a first and a second word length, the second word length longer than the first, the first word length is the same as a data path width of the pipeline (410, 425). Execution of operations on the operands of the second word length requires multiple cycles in at least one execution stage (412, 414) of the pipeline. An instruction decoder (404) decodes subcommands of a sequence of VLIW instructions into pipeline subcommands, and dispatches these to the first and second pipelines (410, 425), the instruction decoder (404) injects at least one helper subcommand into the first pipeline (410) when a first subcommand of the VLIW instruction operates on operands of the second word length. The instruction decoder also inserts no-operation helper subcommands into the second pipeline (425) when necessary to ensure that information associated with the first subcommand enters a trap stage (422) of the first pipeline (410) synchronously with information associated with a second subcommand of the same VLIW instruction and dispatched to the second pipeline (425) reaching a trap stage (430) of the second pipeline (425). These no-operation helper subcommands maintain synchronous arrival of information at the trap stages (422, 425) even if the first subcommand operates on operands of the second word length and the second subcommands operates on operands of the first word length. |
