| 摘要 |
A semiconductor memory device (10) having a normal mode of operation and a test mode of operation is provided. The semiconductor memory device (10) can include a plurality of banks (100A to 100D). A bank (100A) may have a plurality of plates (PLT). In the normal mode of operation a row of plates (11020, 11021, . . . 11027) may be activated. In the test mode of operation, half of the row of plates (11020, 11021, . . . 11027) may be activated.
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