SYSTEM AND APPARATUS INCLUDING LOWEST PRIORITY LOGIC TO SELECT A PROCESSOR TO RECEIVE AN INTERRUPT MESSAGE

摘要

One embodiment of the invention includes an apparatus, such as a bridge, for use in connection with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA). The system also includes lowest priority logic to perform the LPIDA to select which of the processors is to receive an interrupt message based on contents of the remote priority capture logic, the interrupt message being provided to the processor through the processor bus.